1. Field of the Invention
The present invention relates to a display apparatus and a method for driving a display panel thereof. More particularly, the present invention relates to a display apparatus having more uniform induction sensitivity and a method for driving a display panel thereof.
2. Description of Related Art
Among different types of input panel products, an input panel with a sensing film will have a higher cost and a lower transmittance reduced by about 20%. While in embedded input panels, inducing circuits capable of sensing touches are designed depending on characteristics of amorphous-Si, and integrated into a thin film transistor (TFT) array process of a thin film transistor-liquid crystal display (referred to as TFT-LCD). By comparison, embedded input panels have the advantages of low cost and better optical properties, so they have gradually replaced the input panels with a sensing film.
In the design of the embedded input panels, the inducing circuits are added on the original pixel layout of the display panel, so the functions of the inducing circuits must be ensured while not affecting the original optical properties. In other words, the inducing circuits must be compatible with the original panel design, thereby maintaining the display quality and realizing the input function. FIG. 1 is a schematic view of a configuration of inducing circuits of a conventional embedded input panel and gate line signals thereof. Referring to FIG. 1, a display panel is denoted by 100. Inducing circuits are denoted by 102. Gate lines are denoted by G1-GN. Inducing signal readout lines are denoted by R1-RM. A signal processing circuit is denoted by 104. Gate line signals of the gate lines G1-GN are denoted by SG1-SGN. A gate pulse is denoted by 106. A blanking time between two frames is denoted by TB, which will be described below.
Referring to FIG. 1 again, the inducing circuits 102 in FIG. 1 are disposed according to the arrangement of the original pixels (not shown), so the inducing circuits 102 are also referred to as pixel inducing circuits. In FIG. 1, each pixel works together with one inducing circuit 102, and each inducing circuit 102 is coupled to one of the gate lines and one of the inducing signal readout lines. The inducing circuits 102 output an inducing signal to the inducing signal readout lines once receiving a gate pulse, such that the signal processing circuit 104 processes the readout inducing signal.
Generally speaking, the inducing circuits 102 may be realized by two circuit structures respectively as shown in FIG. 2 and FIG. 3. FIG. 2 shows a common charge inducing circuit. Referring to FIG. 2, the charge inducing circuit is denoted by 200. The bias is denoted by VB. The inducing signal readout line is denoted by RX. The gate line is denoted by GX. The charge inducing circuit 200 consists of a TFT 202 for sensing, a TFT 204 serving as a switch, and capacitors 206-210. FIG. 3 shows a common current inducing circuit. Referring to FIG. 3, the current inducing circuit is denoted by 300. The bias is denoted by VB. The inducing signal readout line is denoted by RX. The gate line is denoted by GX. The current inducing circuit 300 consists of a TFT 302 for sensing, a TFT 304 serving as a switch, and capacitors 306-310.
Referring to FIG. 1 again, it can be known from the gate pulse timing in FIG. 1 that in each frame, gate lines in the display panel 100 are sequentially driven in the manner of gate lines G1-GN. Between two adjacent frames, in a short time period, no gate pulse drives the gate lines, which is the previously mentioned blanking time TB. In other words, the blanking time TB can be defined as the time between after the last driven gate line signal SGN closed of the first frame and before the first driven gate line signal SG1 opened of the second frame, the first frame and the second frame are adjacent frames. During the blanking time TB, as all the gate line signals SG1-SGN are in a low voltage level state, the voltage level of the inducing signal are greatly changed, and thus the induction sensitivity of the embedded input panel may be non-uniform, which will be explained with reference to FIG. 4.
FIG. 4 illustrates a relationship between the inducing signal level and the gate line signals SG1-SGN on one of the inducing signal readout lines in FIG. 1. Referring to FIG. 4, the inducing signal level on the inducing signal readout line is denoted by VROUT. The SG1-SGN and symbol TB denote the same as those in FIG. 1. As the gate pulses of the gate line signals SG1-SGN are generated at different time, the gate lines G1-GN are sequentially driven according to the generation sequence of the gate pulses. Since the time difference between driving two adjacent gate lines is extremely small, the inducing signal level VROUT on the inducing signal readout lines remains substantial constant (here, the constant inducing signal may also be referred to as a background signal). The parts denoted by 402 or 404 on the inducing signal level VROUT reflect that the inducing circuits 102 senses an input signal.
During the blanking time TB, although the gate line signals SG1-SGN are in a low level state, a current leakage of the inducing circuits 102 occurs, such that the inducing signal level VROUT is lowered. When the next frame starts, the inducing signal level VROUT is gradually raised to a normal state once again because the gate lines G1-GN is sequentially driven. However, in the course of raising the level once again, if the inputs from the user happen again, the input signals as shown by 406 or 408, as the inducing signal level VROUT has not returned to the normal state yet, the identification accuracy of the first several gate lines of the next frame when turning on will not be influenced, thus degrading the induction sensitivity of the top portion of the embedded input panel. In this manner, the overall induction sensitivity of the embedded input panel is non-uniform.